High performance automotive radar sensors for autonomous driving need to comply with stringent angular resolution requirements. Angular resolution relates directly to the system total antenna aperture, which in turn normally relates to the number of receive antennas and their localization with respect to each other.
To avoid so-called grating lobes in the angular response (i.e. false target detection at certain angular positions), it is necessary that the antennas be located not further than λ/2 from each other, with λ being the wavelength of carrier signal. In practice, aperture sizes in the range of 6λ to 10λ are common, which combined with the λ/2 criteria for each antenna leads to a number of antenna receiver elements between 12 and 20.
FIG. 1 shows an image of an example radar sensor comprising 12 RX antennas attached to three separate RX chips. A TX chip can be seen on the left part of the image, while the three RX chips can be seen in the central part of the image. Each of the 12 RX antenna elements connects to a separate receiver channel, with the receiver channels being distributed across the three RX chips.
For a complete system realization, each RX antenna signal must be down-converted to baseband and then transferred to the digital domain using a respective analog-to-digital converter (ADC). Both the local oscillator signal used to down-convert the RX antenna signals and the sampling clock signal of the different ADCs must be phase-coherent and stable with respect to the corresponding signals of the other ADCs. Otherwise, errors in the angular position estimates are introduced during signal processing in the base-band, and the advantages of using a large array to increase sensor angular resolution may be lost.
Several integrated circuit chip-sets are available, offering down-conversion operation and flexibility for creating different sizes of antenna arrays. In addition to the example shown in FIG. 1, further example configurations of RX and TX channels supported by combinations of available chips are presented in FIG. 2. However these circuits do not offer integrated ADCs and as such do not deal with the requirement for ADC clock synchronization discussed above.